Decoding the CFSR register on ARM Cortex-M
The CFSR (Configurable Fault Status Register, 0xE000ED28) is the single most useful register for diagnosing an ARM Cortex-M fault. It is three sub-registers packed into 32 bits.
UsageFault (UFSR, bits 16-31)
DIVBYZERO (26), UNALIGNED (25), NOCP (19, coprocessor/FPU not enabled), INVPC (18), INVSTATE (17, bad Thumb state / corrupt function pointer), UNDEFINSTR (16).
BusFault (BFSR, bits 8-15)
BFARVALID (15), LSPERR (13), STKERR (12, stacking — stack overflow), UNSTKERR (11), IMPRECISERR (10, async), PRECISERR (9, BFAR valid), IBUSERR (8).
MemManage (MMFSR, bits 0-7)
MMARVALID (7), MLSPERR (5), MSTKERR (4), MUNSTKERR (3), DACCVIOL (1), IACCVIOL (0). When MMARVALID/BFARVALID are set, MMFAR/BFAR hold the faulting address.