ARM Cortex-M HardFault: how to diagnose and fix it
A HardFault is the catch-all exception on ARM Cortex-M. Most HardFaults are actually an escalated configurable fault (MemManage, BusFault, or UsageFault) — so the real story is in the fault status registers, not the HardFault itself.
Step 1 — check HFSR for escalation
Read HFSR (0xE000ED2C). If bit 30 (FORCED) is set, a configurable fault escalated to HardFault — decode CFSR next. If bit 1 (VECTTBL) is set, it was a vector table read error (bad VTOR or boot config).
Step 2 — decode CFSR
CFSR (0xE000ED28) packs UsageFault (bits 16-31), BusFault (8-15) and MemManage (0-7). Common culprits: STKERR (bit 12) = bus fault while stacking on exception entry, the classic stack-overflow signature; IMPRECISERR (bit 10) = asynchronous write-buffer error where the stacked PC is not the faulting instruction; UNDEFINSTR (bit 16) = undefined instruction, often an FPU op on a no-FPU core.
Step 3 — use the stacked frame
On exception entry the core stacks {R0-R3, R12, LR, PC, xPSR}. The stacked PC is the instruction that faulted (unless IMPRECISERR). Feed that PC to addr2line to get file:line.